Eden Scott has an excellent opportunity for a Principal FPGA Verification Engineer to join a leading defence technology company, based in Edinburgh.

What type of work would I be involved in?

You will be implementing FPGA test benches for an all-new Radar Processor, destined for a fast jet platform. The key duties of the role will be to plan, design and write code to implement complex test benches for multiple FPGA designs. Reporting to the firmware team lead, you will work as part of a larger firmware team focused on delivering multiple FPGA designs for the Radar Processor. You will provide verification support across multiple designs and coach other engineers on constrained random verification.

Great work life balance.

Life shouldn’t be all work and no play. That’s why our client offers brilliant benefits like half days on Fridays, flexible hours, gym memberships, and many other incentives to make life great. Not to forget, an award-winning pension scheme.

Note, that due to the nature of the tasks involved, you will have to achieve full SC security clearance, and may need to satisfy further UK eyes only and ITAR conditions.

What you will do

As Principal Firmware Verification Engineer you will be responsible for;

  • Development of firmware verification plans and supporting documentation.
  • Design and implementation of test benches and supporting verification IP.
  • Identifying common test components that can be used across multiple designs.
  • Mentoring and coaching of more junior team members.
  • Ensuring that test benches follow the company firmware process.

Where is the role based?

You will be working within a vibrant capital city, with excellent transport links and walking distance to various key destinations. Free parking is provided on site.

What we are looking for

You will ideally have experience in the following areas;

  • Proficient in SystemVerilog / UVM.
  • Developing verification plans from requirements.
  • Coverage-driven constrained random test environments.
  • Working to a structured firmware process such as RTCA DO-254 or similar.
  • Debugging complex test benches and firmware designs.
  • Exposure to Model Driven Engineering and its inclusion in constrained random test benches.
  • Ability to communicate effectively across different disciplines both verbally and in written form.
  • Ability to work on own or as part of a team including engineers from other disciplines.
  • Familiarity with Mentor Graphics FPGA development tools including Questa and Verification Run Manager. HDL Designer is an advantage.


  • First or second degree (BSc, BEng, MEng, MSc, PhD, EngD) in Electrical & Electronic Engineering (preferable) or related science (eg Physics).

To learn more about this exciting opportunity, please contact Derek Polowyj for a confidential chat by mobile on 07305 954287 or by email at

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